1. Field of the Invention
The present invention relates to an address generator, interleave unit, deinterleave unit, and transmission unit, and more particularly, is preferably applied to a radio communications system such as a portable telephone system.
2. Description of the Related Art
A radio communication system of this type is so structured that an area of communication service is divided into cells of a desired size and a base station is installed as a fixed radio station within each of the cells, and a portable telephone set serving as a mobile radio station communicates by radio with the base station of the cell in which it is located, thus implementing a so-called cellular system.
One of various communication systems between a portable telephone set and a base station is the code division multiple access (CDMA) system. The CDMA system assigns on the transmission side inherent pseudo random noise sequence (PN) codes composed of pseudo random series codes to each communication line and multiplies the PN code by the primary modulated signal, thereby diffusing the PN code over a wider bandwidth than the original frequency bandwidth (hereinafter referred to as the spread spectrum), and transmits the secondary modulated waves which have undergone the spread spectrum processing.
Such cellular system mobile station of the CDMA system adds cyclic redundancy check (CRC) codes to audio data at the time of transmission, performs convolutional coding (processing up to here is called encoding), and then, supplies thus obtained series of transmit symbols to an interleave processing circuit (hereinafter, referred to as an interleaver). The interleaver stores the series of transmit symbols in an internal memory in a prescribed write order, and reads out the series of transmit symbols in a read order different from the write order to rearrange the order of symbols at random, that is, performs interleave processing. The series of transmit symbols interleaved is modulated in a prescribed method and is transmitted as an analog transmit signal.
In addition, in the mobile station, each symbol of a series of receive symbols generated by converting the receive signal received at the time of reception into a digital signal is stored in the internal memory in a write order having the same pattern as the transmission side, and is read out in a read order different from the write order, to restore the order of symbols (hereinafter, referred to as deinterleaver). After this, the mobile station performs the Viterbi decoding and then error detection through the CRC codes.
In this case where the series of transmit symbols which have undergone the convolutional coding by the mobile station at the time of transmission does not have errors at random (uniform) in the transmission path but tends to cause burst (local) errors. If such burst errors exceed the error correction capability of the corresponding section, some errors remain uncorrected. To prevent such troubles, errors in the transmission path are distributed, so that the receiving side can efficiently perform error correction processing, by applying interleave processing to the series of transmit symbols.
When the above interleave processing is performed, in the interleaver 1 shown in FIG. 1, transmit symbol series data D16 which has been subjected to convolutional coding processing is supplied as input data to a first interleave memory 2 and a second interleave memory 3, eight bits by eight bits in parallel.
A memory switching controller 4 outputs a write address WA1 generated by a write address counter 5 to only the first interleave memory 2 via a first address selector 6. Accordingly, the first interleave memory 2 writes the transmit symbol series data D16 into a predetermined area in an eight-bit unit according to the write address WA1.
Although the write address WA1 is also outputted to a second address selector 10, the write address WA1 is not outputted to the second interleave memory 3 from the second address selector 10 because the second address selector 10 outputs read addresses under the control of the memory switching controller 4.
Next the memory switching controller 4 transmits a read address RA0 generated by a read address counter 8 of a read address generator 7 to an address conversion ROM 9. The address conversion ROM 9 converts the read address RA0 to a new read address RA1 specified to rearrange the write order to a random order according to the read address RA0, then outputs the address RA1 to only the first interleave memory 2 via the first address selector 6.
Here the read address RA1 is also outputted to the second address selector 10. The read address RA1 is not outputted to the second interleave memory 3 from the second address selector 10 because the second address sector 10 outputs the write address WA1 under the control of the memory switching controller 4.
The first interleave memory 2 reads the just written transmit symbol series data D16 in an eight-bit unit according to the read address RA1 and outputs the transmit symbol series data D16 as interleaved converted data D2 via a data selector 11. Since the read address RA1 is converted to a read address different from that used for write processing by the address conversion ROM 9, the interleaved converted data D2 is outputted.
The memory switching controller 4, while reading the interleaved converted data D2 from the first interleave memory 2, outputs the write address WA1 from the second address selector 10 to the second interleave memory 3 to write the next transmit symbol series data D16 in the predetermined area of the second interleave memory 3 in a eight-bit unit according to the write address WA1.
When the memory switching controller 4 finishes reading the converted data D2 from the first interleave memory 2, it switches the second address selector 10 to output the read address RA1, which is outputted from the read address generator 7, to the second interleave memory 3 via the second address selector 10. Accordingly, the second interleave memory 3 reads the just written transmit symbol series data D16 in an eight-bit unit according to the read address RA1 and outputs the transmit symbol series data D16 as interleaved converted data D3 via the data selector 11.
At this time, the memory switching controller 4, while reading interleaved converted data D3 from the second interleave memory 3, outputs the write address WA1 from the first address selector 6 to the first interleave memory 2. In this way, the memory switching controller 4 is so structured that, while it is reading the interleaved converted data D2 from the first interleave memory 2, it writes the transmit symbol series data D16 into the second interleave memory 3, and further, while it is reading the interleaved converted data D3 from the second interleave memory 3, writes the transmit symbol series data D16 into the first interleave memory 2, thus efficiently interleaving the input transmit symbol series data D16.
In this way, the conventional interleaver 1 needs to be provided with the address conversion ROM 9 in the read address generator 7 for interleave processing. The mobile station as a whole requires a deinterleaver (not shown) provided with the address conversion ROM 9 similar to that of the interleaver 1, in addition to the interleaver 1. As a result, the mobile station has a problem the amount of data to be stored in the address conversion ROM9 is large as the patterns of the write/read address patterns which are used for interleave/deinterleave processing increase with increase of data, resulting in larger circuit scale.
As shown in FIG. 2 where the same numerals are applied to parts corresponding to FIG. 1, in the interleaver 120, a read address RA3 generated by a read address counter 23 in a read address generator 121 is outputted to a first address selector 6 and a second address selector 10 and the read address RA3 is fed back to an address control circuit 22.
As a result, the address control circuit 22 newly generates the read address RA3 which has predetermined intervals by adding a predetermined value on the basis of the fed back read address RA3. The address control circuit 22 outputs the read address RA3 to the first address selector 6 and the second address selector 10 via the read address counter 23 and feeds back the read address RA3 to the address control circuit 22 again.
In this case also, the mobile station as a whole requires the read address generator 121 comprising the address control circuit 22 and the read address counter 23 in the interleaver 120, and requires a similar address control circuit and read address counter in a read address generator of a deinterleaver (not shown). Therefore, there was a problem that the processing of the address control circuit 22 become complicated as the patterns of the write/read address which are used for interleave/deinterleave processing increase.
In the interleavers 1 and 120, arrangement used when data is written into the first interleave memory 2 and the second interleave memory 3 may not be simply configured in eight-bit unit (one byte) depending on the interleave pattern. Such a case has a problem that a memory cannot be used efficiently.
Further, when the memory switching controller 4 executes interleave processing using the first interleave memory 2 and the second interleave memory 3 alternately, a plurality of interleave memories have to be provided. This is troublesome in that the total memory capacity increases, thus requiring larger circuits.
On the other hand, when only the first interleave memory 4 is used to execute interleave processing, the memory switching controller 4 first transmits the frame xe2x80x9c0xe2x80x9d data read from the first interleave memory 2 in read order different from the write order, which is used at the time of storing, to the transmitter 12 one bit by one bit. The memory switching controller 4 is so structured that it reads the last one-bit data of frame xe2x80x9c0xe2x80x9d from the first interleave memory 2 and outputs the data to the transmitter 12, then reads the first one-bit data of the next frame xe2x80x9c1xe2x80x9d from the first interleave memory 2 without interruption and outputs the data to the transmitter 12.
However, there occurs a problem that, for a very short period of time from when the memory switching controller 4 reads the last one-bit data of frame xe2x80x9c0xe2x80x9d from the first interleave memory 2 and outputs the data to the transmitter 12 until it reads the first one-bit data of the next frame xe2x80x9c1xe2x80x9d from the first interleave memory 2, the memory switching controller 4 may fail to perform encoding for storing into the first interleave memory 4 all transmit symbol series generated by adding CRC codes and applying convolutional coding to the audio data corresponding to the next frame xe2x80x9c1.xe2x80x9d
Accordingly, there was a problem that, to perform encoding for the very short period of time, a faster clock has to be used, causing greater consumed power, or additional memory for encoding for the very short period of time has to be separately provided, thus requiring larger circuits.
In view of the foregoing, an object of this invention is to provide an address generator, interleave unit, and deinterleave unit which can generate addresses for outputting data in a randomly rearranged form with a simple construction.
Another object of the invention is to provide a transmission unit and a transmission method which can reduce memory capacity required for interleave processing.
The foregoing objects and other objects of the invention have been achieved by the provision of an address generator for generating addresses of an prescribed order predetermined for storage means in the case of writing data to the storage means or reading data from the storage means. The address generator comprises a first address data generating means for generating a plurality of first address data which have predetermined address intervals, a second address data generating means for generating second consecutive address data for the first address data every address interval, and an addition means for generating addresses which have predetermined intervals in order by sequentially adding the second address data to each piece of the first address data. This allows addresses, which have predetermined intervals, to be generated in order by using only the first address data generating means, the second address data generating means and the addition means with a simple construction, even when the address patterns for rearranging and outputting data in interleaved order increase.
Further, the present invention provides an interleave unit for rearranging and outputting for each frame in a random order symbols of transmit symbol series generated by coding original data. The interleave unit has an address generator comprising a first address data generating means for generating a plurality of first address data which have predetermined address intervals, a second address data generating means for generating second consecutive address data for the first address data every address interval, and an addition means for generating addresses which has predetermined intervals in order by seguentially adding the second address data to each piece of the first address data, and a control means for rearranging and outputting symbols of transmit symbol series in interleaved order by sequentially assigning addresses, which have predetermined intervals, to transmit symbol series. This allows addresses, which have predetermined intervals, to be generated in order by using the first address data generating means, the second address data generating means and the addition means with a simple construction, even the address patterns used by the interleave unit for rearranging and outputting transmit symbol series in interleaved order increase.
Further, the present invention provides a deinterleave unit for receiving transmit signals, in which the transmit signals comprising transmit data obtained by rearranging and outputting for each frame in interleaved order symbols of transmit symbol series generated by coding original data is subjected to a prescribed transmission processing and transmitted, and for rearranging symbols of received symbol series retrieved from the received signals into the original order. The deinterleave unit has an address generator comprising a first address data generating means for generating a plurality of first address data which have predetermined address intervals, a second address data generating means for generating second consecutive address data for the first address data every address interval, and an addition means for generating addresses, which have predetermined intervals, in order by sequentially adding the second address data to each piece of the first address data, and a control means for rearranging and outputting symbols of received symbol series into original order by sequentially assigning addresses, which have predetermined intervals, to received symbol series. This allows addresses, which have predetermined intervals, to be generated in order by using only the first address data generating means, the second address data generating means and the addition means with a simple construction, even when the address patterns used by the deinterleave unit for rearranging and outputting received symbol series in interleaved order increase.